LTC6991HS6 データシートの表示（PDF） - Linear Technology
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LTC6991HS6 Datasheet PDF : 24 Pages
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LTC6991
Applications Information
Self-Resetting Circuits
The RST pin has hysteresis to accommodate slow-changing
input voltages. Furthermore, the trip points are proportional
to the supply voltage (see Note 6 and the RST Threshold
Voltage vs Supply Voltage curve in Typical Performance
Characteristics). This allows an RC time constant at the
RST input to generate a delay that is nearly independent
of the supply voltage.
A simple application of this technique allows the LTC6991
output to reset itself, producing a well-controlled pulse
once each cycle. Figures 13a and 13b show circuits that
produce approximately 1µs pulses once a minute. The
only difference is in the POL bit setting, which controls
whether the pulse is positive or negative.
Voltage Controlled Frequency
With one additional resistor, the LTC6991 output frequency
can be manipulated by an external voltage. As shown in
Figure 14, voltage VCTRL sources/sinks a current through
RVCO to vary the ISET current, which in turn modulates the
output frequency as described in Equation (3).
fOUT
=
1MHz • 50kΩ
1024 •NDIV •RVCO
•
1+
RVCO
RSET
–
VCTRL
VSET
(3)
Digital Frequency Control
The control voltage can be generated by a DAC (digital-
to-analog converter), resulting in a digitally-controlled
frequency. Many DACs allow for the use of an external
reference. If such a DAC is used to provide the VCTRL
voltage, the VSET dependency can be eliminated by buffer-
ing VSET and using it as the DAC’s reference voltage, as
shown in Figure 15. The DAC’s output voltage now tracks
any VSET variation and eliminates it as an error source.
The SET pin cannot be tied directly to the reference input
of the DAC because the current drawn by the DAC’s REF
input would affect the frequency.
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
16
RPW
2.26k
CPW
470pF
RST
OUT
LTC6991
GND
V+
RSET
715k
SET
DIV
OUT
2.25V TO 5.5V
R1
0.1µF
1M
R2
392k
tPULSE
= –RPW
•
CPW
•
In
1–
VRST(RISING)
V+
tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61)
tPULSE ≈ 1µs
1µs PULSE WIDTH
60 SECONDS
6991 F13a
Figure 13a. Self-Resetting Circuit (DIVCODE = 4)
RPW
2.26k
CPW
470pF
RST
OUT
LTC6991
GND
V+
RSET
715k
SET
DIV
OUT
2.25V TO 5.5V
R1
0.1µF
392k
R2
1M
tPULSE = –RPW • CPW • In
VRST(FALLING)
V+
tPULSE ≈ –2.26kΩ • 470pF • In(0.43)
tPULSE ≈ 0.9µs
0.9µs PULSE WIDTH
60 SECONDS
6991 F13b
Figure 13b. Self-Resetting Circuit (DIVCODE = 11)
RST
OUT
LTC6991
GND
V+
RVCO
VCTRL
SET
DIV
RSET
V+
C1
0.1µF R1
R2
6991 F14
Figure 14. Voltage-Controlled Oscillator
6991f
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