LV5768V データシートの表示（PDF） - SANYO -> Panasonic

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LV5768V

1-channel Step-down Switching Regulator

SANYO -> Panasonic 

LV5768V

• Caution for pattern layout

C1: input capacitor

When the IC performs switching, ripple current flows into the input capacitor of DC-DC converter. The capacitor of

input should be connected adjacent to the power IC and minimize the inductance from pattern layout. C1 should be

connected adjacently to VIN pin of the IC and Q1 (high side FET- drain). If implementation to IC side is not feasible,

insert adjacently to Q1.

C7 (bypass capacitor connected to VIN pin of the IC) should be connected adjacently to VIN pin and GND pin. In

rare cases, intensive ringing may occur in the VIN pin by connecting bypass capacitor. The recommendation value is

1000pF.

Q1, Q2 (D1): external FET

Both high and low sides are driven by Nch-MOSFET. In Q1, a transition of SW node takes place between VIN and

GND by turn on and off, where high frequency noise occurs. The noise affects the surrounding pattern layouts and

parts. The high/ low side gate and SW node should be laid out as fat and short as possible without connecting all the

way to HDRV, LDRV and SW pins of the IC. HDRV, LDRV and SW pins should be shielded with GND to prevent

influence from noise.

When high side FET is turned on, current path is as follows: VIN + (C1) --> inductor (L) --> VOUT (load) -->

PGND --> GND. When low side FET is turned on, current path is as follows: inductor (L) --> VOUT (load) -->

PGND. By minimizing the area of current path and keeping the pattern layout fat and short, noise is eliminated and

error operation is prevented. Hence, Q1, Q2, D1, C1 and C9 should be implemented nearby.

R5,C6: ILIM (overcurrent limiter set pin)

ILIM pin detects overcurrent which is used as set point where current limit comparator in the IC starts operation. The

overcurrent limiter is adjustable by the resistor between ILIM pin and VIN pin. When the voltage of SW pin

becomes lower than that of ILIM pin, current limit comparator functions and turns off the high side MOSFET. This

operation is reset at every PWM pulse.

To filter unwanted noise, C6 should be connected in parallel to the set resistor (the recommendation is 1000pF). R5

and C6 should be implemented adjacently to the VIN side of the IC. If they are apart from the VIN side, detection

precision for overcurrent point may be deteriorated.

Small signal system: part for FB, COMP, EN, CBOOT, VDD and SS pins.

The parts should be implemented adjacently to the IC and be connected as short as possible. Also the GND of the

parts should have common GND pattern as the IC. FB pattern layout should not be under nor nearby the inductor or

SW node. This must be complied to avoid error operation.

PS No.A2093-14/15

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