M24C16-FTW20I/90 データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M24C16-FTW20I/90

16-Kbit serial I2C bus EEPROM

STMicroelectronics 

Instructions

5

Instructions

M24C16-W M24C16-R M24C16-F

5.1

Write operations

Following a Start condition the bus master sends a device select code with the R/W bit (RW)

reset to 0. The device acknowledges this, as shown in Figure 6, and waits for the address

byte. The device responds to each address byte with an acknowledge bit, and then waits for

the data byte.

Table 3. Address byte

A7

A6

A5

A4

A3

A2

A1

A0

When the bus master generates a Stop condition immediately after a data byte Ack bit (in

the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write

cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal

Write cycle.

After the Stop condition and the successful completion of an internal Write cycle (tW), the

device internal address counter is automatically incremented to point to the next byte after

the last modified byte.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does

not respond to any requests.

If the Write Control input (WC) is driven High, the Write instruction is not executed and the

accompanying data bytes are not acknowledged, as shown in Figure 7.

14/39

DocID023494 Rev 6

Share Link: