M25P05-AVMP6TG データシートの表示（PDF） - Numonyx -> Micron

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M25P05-AVMP6TG

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

Instructions

M25P05-A

When the status register write disable (SRWD) bit of the status register is set to ‘1’, two

cases need to be considered, depending on the state of Write Protect (W):

● If Write Protect (W) is driven High, it is possible to write to the status register provided

that the write enable latch (WEL) bit has previously been set by a write enable (WREN)

instruction

● If Write Protect (W) is driven Low, it is not possible to write to the status register even if

the write enable latch (WEL) bit has previously been set by a write enable (WREN)

instruction (attempts to write to the status register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the block protect (BP1, BP0) bits of the status register, are

also hardware protected against data modification.

Regardless of the order of the two events, the hardware protected mode (HPM) can be

entered:

● by setting the status register write disable (SRWD) bit after driving Write Protect (W)

Low

● or by driving Write Protect (W) Low after setting the status register write disable

(SRWD) bit.

The only way to exit the hardware protected mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can

never be activated, and only the software protected mode (SPM), using the block protect

(BP1, BP0) bits of the status register, can be used.

Figure 11. Write status register (WRSR) instruction sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

Status

register in

D

76543210

High Impedance

MSB

Q

AI02282D

24/52

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