M25P05-AVMB6TP データシートの表示（PDF） - Numonyx -> Micron

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M25P05-AVMB6TP

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

M25P05-A

Instructions

6.7

Read data bytes at higher speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the read

data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit

being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.

There is no address roll-over; when the highest address (0FFFFh) is reached, the

instruction should be terminated.

The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip

Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read

data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle

is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence

and data-out sequence

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

C

Instruction

24-bit address

D

23 22 21

3210

High Impedance

Q

S

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

C

Dummy byte

D

76543210

DATA OUT 1

DATA OUT 2

Q

76543210765432107

MSB

MSB

MSB

1. Address bits A23 to A16 must be set to 00h.

AI04006

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