M25P05-AVZW6TP データシートの表示（PDF） - Numonyx -> Micron

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M25P05-AVZW6TP

512-Kbit, serial flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

M25P05-A

Instructions

6.10

Bulk erase (BE)

The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write

enable (WREN) instruction must previously have been executed. After the write enable

(WREN) instruction has been decoded, the device sets the write enable latch (WEL).

The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)

is driven High, the self-timed bulk erase cycle (whose duration is tBE) is initiated. While the

bulk erase cycle is in progress, the status register may be read to check the value of the

write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk

erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the write enable latch (WEL) bit is reset.

The bulk erase (BE) instruction is executed only if both block protect (BP1, BP0) bits are 0.

The bulk erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 16. Bulk erase (BE) instruction sequence

S

01234567

C

Instruction

D

AI03752D

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