M25P10-AVMB3TP/X データシートの表示（PDF） - Numonyx -> Micron

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M25P10-AVMB3TP/X

1 Mbit, serial Flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

M25P10-A

Instructions

Table 4. Instruction set

Instruction

Description

One-byte instruction Address Dummy Data

code

bytes bytes bytes

WREN Write Enable

0000 0110 06h

0

WRDI

RDID(1)

Write Disable

Read Identification

0000 0100 04h

0

1001 1111 9Fh

0

RDSR Read Status Register

0000 0101 05h

0

WRSR Write Status Register

0000 0001 01h

0

READ Read Data Bytes

0000 0011 03h

3

FAST_READ

Read Data Bytes at Higher

Speed

0000 1011 0Bh

3

PP

Page Program

0000 0010 02h

3

SE

Sector Erase

1101 1000 D8h

3

BE

Bulk Erase

1100 0111 C7h

0

DP

Deep Power-down

1011 1001 B9h

0

Release from Deep Power-

down, and Read Electronic

0

RES

Signature

1010 1011 ABh

Release from Deep Power-

down

0

0

0

0

0

0

1 to 3

0

1 to ∞

0

1

0

1 to ∞

1

1 to ∞

0 1 to 256

0

0

0

0

0

0

3

1 to ∞

0

0

1. The Read Identification (RDID) instruction is available in products with process technology code X and Y

(see application note AN1995).

6.1

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector

Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figure 7. Write Enable (WREN) instruction sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

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