24512 データシートの表示（PDF） - STMicroelectronics

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24512

512-Kbit serial I²C bus EEPROM

STMicroelectronics 

M24512-R, M24512-W, M24512-DR

Device operation

3.16

Current Address Read (in memory array)

For the Current Address Read operation, following a Start condition, the bus master only

sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges

this, and outputs the byte addressed by the internal address counter. The counter is then

incremented. The bus master terminates the transfer with a Stop condition, as shown in

Figure 10, without acknowledging the byte.

3.17

Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The

bus master does acknowledge the data byte output, and sends additional clock pulses so

that the device continues to output the next byte in sequence. To terminate the stream of

bytes, the bus master must not acknowledge the last byte, and must generate a Stop

condition, as shown in Figure 10.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output. After the last memory address, the

address counter ‘rolls-over’, and the device continues to output data from memory address

00h.

3.18

Read Identification Page

The Identification Page can be read by issuing an ID Read instruction. This instruction uses

the same protocol and format as the Random Address Read (from memory array) with the

device type identifier defined as 1011b. The MSB address bits A17 to A7 are “don’t care”.

The LSB address bits A6 to A0 define the byte address inside the Identification Page. The

number of bytes to read in the ID page must not exceed the page boundary (e.g. when

reading the Identification Page from location 100d, the number of bytes should be less than

or equal to 28, as the ID page boundary in 128 bytes). If the Identification Page is locked,

the data bytes are read as FFh.

Doc ID 16459 Rev 19

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