M66281FP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M66281FP

5120 x 8-BIT x 2 LINE MEMORY

MITSUBISHI ELECTRIC  

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

• Reading shortest n-cycle write data "n"

(Reading side n-2 cycle ends after the end of writing side n+1 cycle.)

When the reading side n-2 cycle ends before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid.

In the following diagram, end of reading side n-2 cycle and end of writing side n+1 cycle overlap each other. This example can read n cycle

data in the shortest time. When this is the case, reading operation at n-1 cycle is invalid.

WCK

Dn

RCK

Q0n

(Q1n)

n cycle

n+1 cycle

n+2 cycle

n+3 cycle

(n)

n-2 cycle

(n+1)

(n+2)

n-1 cycle

(n+3)

n cycle

invalid

(n)

• Reading longest n-cycle write data "n": 1 line delay

(When writing side n-cycle <2> starts, reading side n cycle <1> then starts.)

Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each

other.

WCK

n cycle <1>*

0 cycle <2>*

n cycle <2>*

Dn

(n-1)<1>*

(n)<1>*

RCK

n cycle <0>*

Q0n

(Q1n)

(n-1)<0>*

(n)<0>*

(0)<2>*

0 cycle <1>*

(n-1)<2>*

(n)<2>*

n cycle <1>*

(0)<1>*

(n-1)<1>*

(n)<1>*

<0>*, <1>* and <2>* indicate value of lines.

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