M28W640FSB データシートの表示（PDF） - STMicroelectronics

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M28W640FSB

32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Boot Block, Secure Flash Memories

STMicroelectronics 

M28W320FST, M28W320FSB, M28W640FST, M28W640FSB

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

Erase aborts if Reset turns to VIL. As data integrity

cannot be guaranteed when the Erase operation is

aborted, the block must be erased again.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 8., Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See APPENDIX C., Figure 19., Erase Flowchart

and Pseudo Code, for a suggested flowchart for

using the Erase command.

Program Command

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program Command.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data

to be written and starts the Program/Erase

Controller.

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 8., Program, Erase

Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See APPENDIX C., Figure 15., Program Flow-

chart and Pseudo Code, for the flowchart for using

the Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0.

Three bus write cycles are necessary to issue the

Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to VIL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See APPENDIX C., Figure 16., Double Word Pro-

gram Flowchart and Pseudo Code for the flow-

chart for using the Double Word Program

command.

Quadruple Word Program Command

This feature is offered to improve the programming

throughput, writing a page of four adjacent words

in parallel.The four words must differ only for the

addresses A0 and A1.

A Quadruple word Program command will be ig-

nored if VPP is not set to VPPH.

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

■ The first bus cycle sets up the Quadruple

Word Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and

the Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to VIL. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See APPENDIX C., Figure 17., Quadruple Word

Program Flowchart and Pseudo Code, for the

flowchart for using the Quadruple Word Program

command.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

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