M32000D4FP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M32000D4FP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

M32000D4AFP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION (3/3)

type

bus

control

(cont.)

interrupt

controller

pin name

__

DC*

name

data complete

______

HREQ

_____

HACK

__

CS

___

SBI

___

INT

hold

hold

acknowledge

chip

select

system

break

interrupt

external

interrupt

I/O

I/O

(Hi-z)

input

output

input

input

input

function

When the M32000D4AFP drives an _e_xternal bus cycle, it

automatically inserts wait cycles until DC is input by the slave

device in the system bus.

When the M32000D4AFP is in the hold state and the internal

DRAM is _ a_ ccessed from an external bus master, the M32000D4AFP

outputs DC to notify to the external bus master that the bus

cycle to the internal DRAM has been completed.

______

Bus right request input pin of the system bus. When HREQ is an

"L" level, the M32000D4AFP switches to the hold state.

Indicates that the M32000D4AFP has switched to the hold state

and releases the bus right of the system bus to the requestor.

Signal input to the M32000D4AFP when it is in the hold state to

request access to the internal DR_A_M from an external bus master.

When an "L"level is input to CS, the M32000D4AFP access

accesses the internal DRAMat the address input via the address

pins.

System break interrupt input pin. The SBI is not masked by the

IE bit in the PSW register. It is also used to return from CPU

sleep mode and to request the start of operation in slave mode.

External interrupt request input pin. It is also used to return from

CPU sleep mode and to request the start of operation the slave

mode.

programm-

PP0, PP1

port

I/O

Two programmable I/O ports.

able I/O port

__

__

* The DC pin becomes an output pin when the CS signal is input to the M32000D4AFP.

8

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