M36DR432CA10ZA61T データシートの表示（PDF） - STMicroelectronics

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M36DR432CA10ZA61T

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 4 Mbit (256K x16) SRAM, Multiple Memory Product

STMicroelectronics 

M36DR432C, M36DR432D

Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles

(TA = –40 to 85°C; VDDF = 1.9V to 2.1V, VPPF = VDDF unless otherwise specified)

Parameter

Min

Max (1)

Typ

Typical after

100k W/E Cycles

Unit

Parameter Block (4 KWord) Erase (Preprogrammed)

2.5

0.15

0.4

s

Main Block (32 KWord) Erase (Preprogrammed)

10

1

3

s

Bank Erase (Preprogrammed, Bank A)

2

6

s

Bank Erase (Preprogrammed, Bank B)

10

30

s

Chip Program (2)

20

25

s

Chip Program (DPG, VPP = 12V) (2)

10

s

Word Program

200

10

10

µs

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or

erase should perform significantly better.

2. Excludes the time needed to execute the sequence for program instruction.

Table 30. Flash Data Polling and Toggle Bits AC Characteristics (1)

(TA = –40 to 85 °C; VDDF = 1.9V to 2.1V)

Symbol

Parameter

Flash

Unit

Min

Max

Chip Enable High to DQ7 Valid (Program, EF Controlled)

10

tEHQ7V

Chip Enable High to DQ7 Valid (Block Erase, EF Controlled)

1

200

µs

10

s

tEHQV

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Block Erase)

10

200

µs

1

10

s

tQ7VQV

Q7 Valid to Output Valid (Data Polling)

0

ns

Write Enable High to DQ7 Valid (Program, WF Controlled)

10

tWHQ7V

Write Enable High to DQ7 Valid (Block Erase, WF

Controlled)

1

200

µs

10

s

tWHQV

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Block Erase)

10

200

µs

1

10

s

Note: 1. All other timings are defined in Read AC Characteristics table.

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