M36W108 データシートの表示（PDF） - STMicroelectronics

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M36W108

8 Mbit (1Mb x8, Boot Block) Flash Memory and 1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product

STMicroelectronics 

M36W108T, M36W108B

SRAM COMPONENT

Device Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write Ar-

ray, Output Disable, Power Down (see Table 13).

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable (W) is at VIH with

Output Enable (G) at VIL, and both Chip Enables

(E1S and E2S) are asserted.

Valid data will be available at the eight output pins

within tAVQV after the last stable address, provid-

ing G is Low, E1S is Low and E2S is High. If Chip

Enable or Output Enable access times are not

met, data access will be measured from the limit-

ing parameter (tE1LQV, tE2HQV, or tGLQV) rather

than the address. Data out may be indeterminate

at tE1LQX, tE2HQX and tGLQX, but data lines will al-

ways be valid at tAVQV (see Table 21, Figure 14,

Figure 15).

Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever

the W and E1S pins are at VIL, with E2S at VIH. Ei-

ther the Chip Enable inputs (E1S and E2S) or the

Write Enable input (W) must be de-asserted dur-

ing address transitions for subsequent write cy-

cles. Write begins with the concurrence of both

Chip Enables being active with W at VIL. A Write

begins at the latest transition among E1S going to

VIL, E2S going to VIH and W going to VIL. There-

fore, address setup time is referenced to Write En-

able and both Chip Enables as tAVWL, tAVE1L and

tAVE2H respectively, and is determined by the latter

occurring edge. The Write cycle can be terminated

by the rising edge of E1S, the rising edge of W or

the falling edge of E2S, whichever occurs first.

If the Output is enabled (E1S=VIL, E2S=VIH and

G=VIL), then W will return the outputs to high im-

pedance within tWLQZ of its falling edge. Care must

be taken to avoid bus contention in this type of op-

eration. Data input must be valid for tDVWH before

the rising edge of Write Enable, or for tDVE1H be-

fore the rising edge of E1S or for tDVE2L before the

falling edge of E2S, whichever occurs first, and re-

main valid for tWHDX, tE1HDX or tE2LDX (see Table

22, Figures 17, 18, 19).

Output Disable. The data outputs are high im-

pedance when the Output Enable (G) is at VIH with

Write Enable (W) at VIH.

Power-Down. The SRAM chip has a Chip Enable

power-down feature which invokes an automatic

standby mode (see Table 21, Figure 16) whenever

either Chip Enable is de-asserted (E1S=VIH or

E2S=VIL).

Data Retention

The SRAM data retention performances as VCCS

go down to VDR are described in Table 23 and Fig-

ures 22, 23. In E1S controlled data retention

mode, minimum standby current mode is entered

when E1S ≥ VCCS – 0.2V and E2S ≤ 0.2V or

E2S ≥ VCCS – 0.2V. In E2S controlled data reten-

tion mode, minimum standby current mode is en-

tered when E2S ≤ 0.2V.

Table 13. SRAM User Bus Operations (1)

Operation

E1S

E2S

W

Read

VIL

VIH

VIH

Write

VIL

VIH

VIL

Output Disable

VIL

VIH

VIH

Power Down

VIH

X

X

X

VIL

X

Note: 1. X = VIL or VIH.

G

DQ0-DQ7

Power

VIL

Data Output

Active

X

Data Input

Active

VIH

Hi-Z

Active

X

Hi-Z

Stand-by TTL

X

Hi-Z

Stand-by TTL/CMOS

14/35

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