M36WT864 データシートの表示（PDF） - STMicroelectronics

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M36WT864

64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512K x16) SRAM, Multiple Memory Product

STMicroelectronics 

M36WT864TF, M36WT864BF

Flash Memory Component

The Flash memory is a 64 Mbit (4Mbit x16) non-

volatile Flash memory that may be erased electri-

cally at block level and programmed in-system on

a Word-by-Word basis using a 1.65V to 2.2V VDD

supply for the circuitry and a 1.65V to 3.3V VDDQ

supply for the Input/Output pins. An optional 12V

VPPF power supply is provided to speed up cus-

tomer programming.

The device features an asymmetrical block archi-

tecture with an array of 135 blocks divided into 4

Mbit banks. There are 15 banks each containing 8

main blocks of 32 KWords, and one parameter

bank containing 8 parameter blocks of 4 KWords

and 7 main blocks of 32 KWords. The Multiple

Bank Architecture allows Dual Operations, while

programming or erasing in one bank, Read opera-

tions are possible in other banks. Only one bank at

a time is allowed to be in Program or Erase mode.

It is possible to perform burst reads that cross

bank boundaries. The bank architecture is sum-

marized in Table 3, and the memory maps are

shown in Figure 5. The Parameter Blocks are lo-

cated at the top of the memory address space for

the M36WT864TF, and at the bottom for the

M36WT864BF.

Each block can be erased separately. Erase can

be suspended, in order to perform program in any

other block, and then resumed. Program can be

suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles using the supply

voltage VDD. There are two Enhanced Factory

programming commands available to speed up

programming.

Program and Erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

The device supports synchronous burst read and

asynchronous read from all blocks of the memory

array; at power-up the device is configured for

asynchronous read. In synchronous burst mode,

data is output on each clock cycle at frequencies

of up to 54MHz.

The device features an Automatic Standby mode.

During asynchronous read operations, after a bus

inactivity of 150ns, the device automatically

switches to the Automatic Standby mode. In this

condition the power consumption is reduced to the

standby value IDD4 and the outputs are still driven.

The Flash memory features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When VPPF ≤ VPPLK all blocks are protected

against program or erase. All blocks are locked at

Power- Up.

The device includes a Protection Register and a

Security Block to increase the protection of a sys-

tem’s design. The Protection Register is divided

into two segments: a 64 bit segment containing a

unique device number written by ST, and a 128 bit

segment One-Time-Programmable (OTP) by the

user. The user programmable segment can be

permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 6, shows the Security Block and

Protection Register Memory Map.

SRAM Component

The SRAM is an 8 Mbit (512Kb x16) asynchronous

random access memory which features a super

low voltage operation and low current consump-

tion with an access time of 70ns. The memory op-

erations can be performed using a single low

voltage supply, 2.7V to 3.3V.

13/92

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