M36W0R6050B1ZAQF データシートの表示（PDF） - STMicroelectronics

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メーカー

M36W0R6050B1ZAQF

64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package

STMicroelectronics 

Package mechanical

6

Package mechanical

M36W0R6050T1, M36W0R6050B1

In order to meet environmental requirements, ST offers the M36W0R6050T1 and

M36W0R6050B1 devices in ECOPACK® packages. These packages have a Lead-free

second-level interconnect. The category of Second-Level Interconnect is marked on the

package and on the inner box label, in compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 6.

Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,

package outline

D

D1

e

SE

E E2 E1

b

BALL "A1"

FE FE1

A

FD

SD

A2

A1

1. Drawing is not to scale.

ddd

BGA-Z42

18/22

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