M41T60 データシートの表示（PDF） - STMicroelectronics

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M41T60

Serial access real-time clock

STMicroelectronics 

Operation

M41T60

2.1.5

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition, a device that gives out a message is called “transmitter”, the receiving device

that gets the message is called “receiver”. The device that controls the message is called

“master”. The devices that are controlled by the master are called “slaves”.

Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low

level put on the bus by the receiver, whereas the master generates an extra acknowledge

related clock pulse.

A slave receiver which is addressed is obliged to generate an acknowledge after the

reception of each byte. Also, a master receiver must generate an acknowledge after the

reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end-of-data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case, the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Figure 5. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

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Doc ID 10396 Rev 13

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