M41TM6TR データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M41TM6TR

Serial Access TIMEKEEPER®

STMicroelectronics 

M41T00

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

TA

Ambient Operating Temperature

–40 to 85

°C

TSTG

Storage Temperature (VCC Off, Oscillator Off)

–55 to 125

°C

VIO

Input or Output Voltages

–0.3 to 7

V

VCC

Supply Voltage

–0.3 to 7

V

IO

Output Current

20

mA

PD

Power Dissipation

0.25

W

Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of

this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Figure 2. SOIC Connections

OSCI

OSCO

VBAT

VSS

M41T00

1

8

2

7

3

6

4

5

AI00531

VCC

FT/OUT

SCL

SDA

The M41T00 clock has a built-in power sense cir-

cuit which detects power failures and automatical-

ly switches to the battery supply during power

failures. The energy needed to sustain the RAM

and clock operations can be supplied from a small

lithium coin cell.

Typical data retention time is in excess of 5years

with a 50mA/h 3V lithium cell. The M41T00 is sup-

plied in 8 lead Plastic Small Outline package.

OPERATION

The M41T00 clock operates as a slave device on

the serial bus. Access is obtained by implementing

a start condition followed by the correct slave ad-

dress (D0h). The 8 bytes contained in the device

can then be accessed sequentially in the following

order:

1.

Seconds Register

2.

Minutes Register

3.

Century/Hours Register

4.

Day Register

5.

Date Register

6.

Month Register

7.

Years Register

8.

Control Register

The M41T00 clock continually monitors VCC for an

out of tolerance condition. Should VCC fall below

VSO, the device terminates an access in progress

and resets the device address counter. Inputs to

the device will not be recognized at this time to

prevent erroneous data from being written to the

device from an out of tolerance system. When VCC

falls below VSO, the device automatically switches

over to the battery and powers down into an ultra

low current mode of operation to conserve battery

life. Upon power-up, the device switches from bat-

tery to VCC at VSO and recognizes inputs.

2/15

Share Link: