M48T59 データシートの表示（PDF） - STMicroelectronics

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M48T59

64 Kbit (8Kb x8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T59, M48T59Y, M48T59V

isters. The user can then load them with the cor-

rect day, date, and time data in 24 hour BCD

format (see Table 12). Resetting the WRITE bit to

a ’0’ then transfers the values of all time registers

(1FF9h-1FFFh) to the actual TIMEKEEPER

counters and allows normal operation to resume.

After the WRITE bit is reset, the next clock update

will occur within approximately one second.

See the Application Note AN923 "TIMEKEEPER

rolling into the 21st century" for information on

Century Rollover.

Note: Upon power-up following a power failure,

both the WRITE bit and the READ bit will be reset

to ‘0’.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

bit is the MSB of the seconds register. Setting it to

a '1' stops the oscillator. The M48T59/59Y/59V in

the DIP package, is shipped from

STMicroelectronics with the STOP bit set to a '1'.

When reset to a '0', the M48T59/59Y/59V oscilla-

tor starts within one second.

Note: It is not necessary to set the WRITE bit

when setting or resetting the FREQUENCY TEST

bit (FT), the STOP bit (ST) or the CENTURY EN-

ABLE bit (CEB).

Calibrating the Clock

The M48T59/59Y/59V is driven by a quartz con-

trolled oscillator with a nominal frequency of

32,768Hz. The devices are tested not to exceed

35 ppm (parts per million) oscillator frequency er-

ror at 25°C, which equates to about ±1.53 minutes

per month. With the calibration bits properly set,

the accuracy of each M48T59/59Y/59V improves

to better than +1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with

temperature (see Figure 10). Most clock chips

compensate for crystal frequency and tempera-

ture shift error with cumbersome trim capacitors.

The M48T59/59Y/59V design, however, employs

periodic counter correction. The calibration circuit

adds or subtracts counts from the oscillator divider

circuit at the divide by 256 stage, as shown in Fig-

ure 9. The number of times pulses are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the value load-

ed into the five bit Calibration byte found in the

Control Register. Adding counts speeds the clock

up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits (D4-D0) in the Control register (1FF8h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

Figure 10. Crystal Accuracy Across Temperature

Frequency (ppm)

20

0

–20

–40

–60

–80

–100

–120

–140

–160

–40 –30 –20 –10 0

∆F

F

= -0.038

ppm

C2

(T

-

T0)2

±

10%

T0 = 25 °C

10 20 30 40 50 60 70 80

Temperature °C

AI00999

11/21

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