M50FW040 データシートの表示（PDF） - STMicroelectronics

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M50FW040

4 Mbit (512Kb x8, Uniform Block) 3V Supply Firmware Hub Flash Memory

STMicroelectronics 

M50FW040

Table 9. Firmware Hub Register Configuration Map

Mnemonic

Register Name

T_BLOCK_LK

T_MINUS01_LK

T_MINUS02_LK

T_MINUS03_LK

T_MINUS04_LK

T_MINUS05_LK

T_MINUS06_LK

T_MINUS07_LK

FGPI_REG

MANUF_REG

DEV_REG

Top Block Lock Register (Block 7)

Top Block [-1] Lock Register (Block 6)

Top Block [-2] Lock Register (Block 5)

Top Block [-3] Lock Register (Block 4)

Top Block [-4] Lock Register (Block 3)

Top Block [-5] Lock Register (Block 2)

Top Block [-6] Lock Register (Block 1)

Top Block [-7] Lock Register (Block 0)

Firmware Hub (FWH) General Purpose Input Register

Manufacturer Code Register

Device Code Register

Memory

Address

FBF0002h

FBE0002h

FBD0002h

FBC0002h

FBB0002h

FBA0002h

FB90002h

FB80002h

FBC0100h

FBC0000h

FBC0001h

Default

Value

01h

01h

01h

01h

01h

01h

01h

01h

N/A

20h

2Ch

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

Table 10. Lock Register Bit Definitions

Bit Bit Name Value

Function

7-3

Reserved

‘1’ Bus Read operations in this Block always return 00h.

2 Read-Lock

‘0’ Bus read operations in this Block return the Memory Array contents. (Default value).

Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is

‘1’ written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following

1 Lock-Down

a Reset (using RP or INIT) or after power-up.

‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default value).

0

Write-Lock

‘1’

Program and Erase operations in this Block will set an error in the Status Register. The

memory contents will not be changed. (Default value).

‘0’ Program and Erase operations in this Block are executed and will modify the Block contents.

Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-7] Lock Reg-

ister (T_MINUS07_LK).

Table 11. General Purpose Inputs Register Definition

Bit Bit Name Value

7-5

Reserved

4

FGPI4

‘1’ Input Pin FGPI4 is at VIH

‘0’ Input Pin FGPI4 is at VIL

3

FGPI3

‘1’ Input Pin FGPI3 is at VIH

‘0’ Input Pin FGPI3 is at VIL

2

FGPI2

‘1’ Input Pin FGPI2 is at VIH

‘0’ Input Pin FGPI2 is at VIL

1

FGPI1

‘1’ Input Pin FGPI1 is at VIH

‘0’ Input Pin FGPI1 is at VIL

0

FGPI0

‘1’ Input Pin FGPI0 is at VIH

‘0’ Input Pin FGPI0 is at VIL

Note: 1. Applies to the General Purpose Inputs Register (FGPI-REG).

Function

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