M50LPW080K データシートの表示（PDF） - STMicroelectronics

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M50LPW080K

8 Mbit (1M x8, Uniform Block) 3V Supply Low Pin Count Flash Memory

STMicroelectronics 

M50LPW080

used. Any other voltage input to VPP will result in

undefined behavior and should not be used.

VPP should not be set to VPPH for more than 80

hours during the life of the memory.

VSS Ground. VSS is the reference for all the volt-

age measurements.

BUS OPERATIONS

The two interfaces have similar bus operations but

the signals and timings are completely different.

The Low Pin Count (LPC) Interface is the usual in-

terface and all of the functionality of the part is

available through this interface. Only a subset of

functions are available through the Address/Ad-

dress Multiplexed (A/A Mux) Interface.

Follow the section Low Pin Count (LPC) Bus Op-

erations below and the section Address/Address

Multiplexed (A/A Mux) Interface Bus Operations

below for a description of the bus operations on

each interface.

Low Pin Count (LPC) Bus Operations

The Low Pin Count (LPC) Interface consists of

four data signals (LAD0-LAD3), one control line

(LFRAME) and a clock (CLK). In addition protec-

tion against accidental or malicious data corrup-

tion can be achieved using two further signals

(TBL and WP). Finally two reset signals (RP and

INIT) are available to put the memory into a known

state.

The data signals, control signal and clock are de-

signed to be compatible with PCI electrical specifi-

cations. The interface operates with clock speeds

up to 33MHz.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command

Interface or Low Pin Count Registers. A valid Bus

Read operation starts when Input Communication

Frame, LFRAME, is Low, VIL, as Clock rises and

the correct Start cycle is on LAD0-LAD3. On the

following clock cycles the Host will send the Cycle

Type + Dir, Address and other control bits on

LAD0-LAD3. The memory responds by outputting

Sync data until the wait-states have elapsed fol-

lowed by Data0-Data3 and Data4-Data7.

See Table 7. and Figure 6. for a description of the

Field definitions for each clock cycle of the trans-

fer. See Table 23. and Figure 11. for details on the

timings of the signals.

Bus Write. Bus Write operations write to the

Command Interface or Low Pin Count Registers. A

valid Bus Write operation starts when Input Com-

munication Frame, LFRAME, is Low, VIL, as Clock

rises and the correct Start cycle is on LAD0-LAD3.

On the following Clock cycles the Host will send

the Cycle Type + Dir, Address, other control bits,

Data0-Data3 and Data4-Data7 on LAD0-LAD3.

The memory outputs Sync data until the wait-

states have elapsed.

See Table 8. and Figure 7. for a description of the

Field definitions for each clock cycle of the trans-

fer. See Table 23. and Figure 11. for details on the

timings of the signals.

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when LFRAME is driven Low,

VIL, during the bus operation; the memory will tri-

state the Input/Output Communication pins,

LAD0-LAD3.

Note that, during a Bus Write operation, the Com-

mand Interface starts executing the command as

soon as the data is fully received; a Bus Abort dur-

ing the final TAR cycles is not guaranteed to abort

the command; the bus, however, will be released

immediately.

Standby. When LFRAME is High, VIH, the mem-

ory is put into Standby mode where LAD0-LAD3

are put into a high-impedance state and the Sup-

ply Current is reduced to the Standby level, ICC1.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

Reset, INIT, is Low, VIL. RP or INIT must be held

Low, VIL, for tPLPH. The memory resets to Read

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset (see Table 13.). If RP or

INIT goes Low, VIL, during a Program or Erase op-

eration, the operation is aborted and the memory

cells affected no longer contain valid data; the

memory can take up to tPLRH to abort a Program

or Erase operation.

Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux) Inter-

face has a more traditional style interface. The sig-

nals consist of a multiplexed address signals (A0-

12/44

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