M58MR016C, M58MR016D
Figure 17. Double Word Program and Tetra Word Program Flowchart and Pseudo code (1)
Start
Write 55h
Command
Write Address 1
& Data 1
Write Address 2
& Data 2
Write Address 3
& Data 3
Write Address 4
& Data 4
Read Status
Register
NO
Suspend
YES
NO
b7 = 1
YES
Suspend
Loop
NO
b3 = 0
VPP Invalid
Error (1, 2)
YES
NO
b4 = 0
Program
Error (1, 2)
YES
b1 = 0
NO
Program to Protected
Block Error (1, 2)
YES
End
DPG instruction:
– write 30h command
– write Address 1 & Data 1 (3)
– write Address 2 & Data 2 (3)
(memory enters read status state after
the Program instruction)
TPG instruction:
– write 55h command
– write Address 1 & Data 1 (4)
– write Address 2 & Data 2 (4)
– write Address 3 & Data 3 (4)
– write Address 4 & Data 4 (4)
(memory enters read status state after
the Program instruction)
do:
– read status register (E or G must be
toggled) if PES instruction given execute
suspend program loop
while b7 = 1
If b3 = 1, VPP invalid error:
– error handler
If b4 = 1, Program error:
– error handler
If b1 = 1, Program to protected block error:
– error handler
AI05244
Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after
a program sequence.
2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
3. Address 1 and address 2 must be consecutive addresses differing only for address bit A0.
4. Address, address 2, address 3 and address 4 must be consecutive addresses differing only for address bit A1-A0.
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