M5M5V216ATP データシートの表示（PDF） - Renesas Electronics
部品番号
コンポーネント説明
メーカー
M5M5V216ATP Datasheet PDF : 9 Pages
| |||
revision-03, 14.Jan.'03
M5M5V216ATP,RT
MITSUBISHI LSIs
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
A 0~16
BC1
and / or
BC2
tsu (A)
tCW
tsu (BC1) or
tsu (BC2)
trec (W)
S
(Note3)
(Note5)
W
(Note3)
DQ1~16
Write cycle (S control mode)
A 0~16
(Note4)
tsu (D) th (D)
DATA IN
STABLE
tCW
(Note3)
(Note3)
BC1
and / or
BC2
(Note3)
tsu (A)
(Note4)
tsu (S)
trec (W)
(Note3)
S
(Note5)
W
(Note3)
(Note4)
tsu (D) th (D)
(Note3)
DQ1~16
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S low , ov erlaps BC1 and/or BC2 low and W low.
Note 5: When the f alling edge of W is simultaneously or priorto the f alling edge of BC1 and/or BC2 or the f alling edge of S,
the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
Share Link: 