M68HC12B データシートの表示（PDF） - Motorola => Freescale

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M68HC12B

M68HC12 Microcontrollers

Motorola => Freescale 

Freescale Semiconductor, Inc.

General Description

Slow-Mode Clock Divider Advisory

• 16-bit pulse accumulator:

– External event counting

– Gated time accumulation

• Pulse-width modulator (PWM):

– 8-bit, 4-channel or 16-bit, 2-channel

– Separate control for each pulse width and duty cycle

– Programmable center-aligned or left-aligned outputs

• Serial interfaces:

– Asynchronous serial communications interface (SCI)

– Synchronous serial peripheral interface (SPI)

– J1850 byte data link communication (BDLC), MC68HC912B32 and

MC68HC12BE32 only

– Controller area network (CAN), MC68HC(9)12BC32 only

• Computer operating properly (COP) watchdog timer, clock monitor, and

periodic interrupt timer

• Slow-mode clock divider

• 80-pin quad flat pack (QFP)

• Up to 63 general-purpose input/output (I/O) lines

• Single-wire background debug mode (BDM)

• On-chip hardware breakpoints

1.3 Slow-Mode Clock Divider Advisory

Current versions of the M68HC12B-series devices include a slow-mode clock

divider feature. This feature is fully described in Section 10. Clock Generation

Module (CGM). The register that controls this feature is located at $00E0. Older

device mask sets do not support the slow-mode clock divider feature. This register

address is reserved in older devices and provides no function.

Mask sets that do not have the slow-mode clock divider feature on the

MC68HC912B32 include: G96P, G86W, and H91F.

Mask sets that do not have the slow-mode clock divider feature on the

MC68HC12BE32 include: H54T and J38M.

Mask sets that do not have the slow-mode clock divider feature on the

MC68HC(9)12BC32 include: J15G.

M68HC12B Family — Rev. 9.0

MOTOROLA

General Description

For More Information On This Product,

Go to: www.freescale.com

Data Sheet

21

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