MACH230-18JI データシートの表示（PDF） - Lattice Semiconductor
部品番号
コンポーネント説明
メーカー
MACH230-18JI Datasheet PDF : 29 Pages
| |||
FINAL
COM’L: -10/15/20 IND: -18/24
MACH230-10/15/20
High-Density EE CMOS Programmable Logic
Lattice Semiconductor
DISTINCTIVE CHARACTERISTICS
84 Pins
128 Macrocells
10 ns tPD Commercial
18 ns tPD Industrial
100 MHz fCNT
70 Inputs
GENERAL DESCRIPTION
The MACH230 is a member of the high-performance
EE CMOS MACH 2 device family. This device has ap-
proximately twelve times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
The MACH230 consists of eight PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity be-
tween the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH230 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
64 Outputs
128 Flip-flops; 4 clock choices
8 “PAL26V16” blocks with buried macrocells
Pin-compatible with MACH130, MACH131,
MACH231, and MACH435
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the reg-
ister can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the soft-
ware. All output macrocells can be connected to an I/O
cell. If a buried macrocell is desired, the internal feed-
back path from the macrocell can be used, which frees
up the I/O pin for use as an input.
The MACH230 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
Publication# 14132 Rev. I Amendment /0
Issue Date: May 1995
Share Link: 