TIMING
◆ Data format
Address Data
D11 D10 D9 D8
0000
1000
0100
1100
0010
1010
0110
1110
0001
1001
0101
1101
0011
1011
0111
1111
X = Don’t care condition
◆ Data format Timing
Selected
DAC
X
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
DAC8
DAC9
DAC10
DAC11
X
X
X
DA9184A.001
September 7, 1998
DAC Data
D7 D6 D5 D4 D3 D2 D1 D0
DAC Output Level
00000000
00000001
00000010
00000011
00000100
00000101
00000110
::::::::
VSS
(VDD-VSS)/256x1+VSS
(VDD-VSS)/256x2+VSS
(VDD-VSS)/256x3+VSS
(VDD-VSS)/256x4+VSS
(VDD-VSS)/256x5+VSS
(VDD-VSS)/256x6+VSS
:
::.:::::
:
1 1 1 1 1 0 0 1 (VDD-VSS)/256x249+VSS
1 1 1 1 1 0 1 0 (VDD-VSS)/256x250+VSS
1 1 1 1 1 0 1 1 (VDD-VSS)/256x251+VSS
1 1 1 1 1 1 0 0 (VDD-VSS)/256x252+VSS
1 1 1 1 1 1 0 1 (VDD-VSS)/256x253+VSS
1 1 1 1 1 1 1 0 (VDD-VSS)/256x254+VSS
1 1 1 1 1 1 1 1 (VDD-VSS)/256x255+VSS
DI
CLK
LD
DAC
OUT
MSB
D11
D10
D9
D8
LSB
D2
D1
D0
6