MAX1214N データシートの表示（PDF） - Maxim Integrated
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MAX1214N Datasheet PDF : 21 Pages
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1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential RL = 100Ω. Limits are for TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low
VIL
Digital Input-Voltage High
VIH
TIMING CHARACTERISTICS
0.2 x AVCC V
0.8 x AVCC
V
CLK-to-Data Propagation Delay
CLK-to-DCLK Propagation Delay
tPDL
tCPDL
Figure 5
Figure 5
2.05
ns
3.95
ns
DCLK-to-Data Propagation Delay
LVDS Output Rise Time
LVDS Output Fall Time
tCPDL - tPDL Figure 5 (Note 3)
tRISE
20% to 80%, CL = 5pF
tFALL 20% to 80%, CL = 5pF
1.8
1.9
2.0
ns
450
ps
450
ps
Output Data Pipeline Delay
tLATENCY Figure 5
11
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
(Note 4)
AVCC
OVCC
IAVCC
IOVCC
PDISS
PSRR
fIN = 100MHz
fIN = 100MHz
fIN = 100MHz
Offset
Gain
1.70 1.80 1.90
V
1.70 1.80 1.90
V
379
410
mA
65
71
mA
799
866
mW
1.8
mV/V
1.5
%FS/V
Note 1: Values at TA ≥ +25°C guaranteed by production test, values at TA < +25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are computed from an end-point curve fit.
Note 3: Parameter guaranteed by design and characterization: TA = -40°C to +85°C.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
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