MAX1213N データシートの表示（PDF） - Maxim Integrated

部品番号

コンポーネント説明

メーカー

MAX1213N

1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications

Maxim Integrated 

1.8V, Low-Power, 12-Bit, 170Msps

ADC for Broadband Applications

Data Clock Outputs (DCLKP, DCLKN)

The MAX1213N features a differential clock output,

which can be used to latch the digital output data with

an external latch or receiver. Additionally, the clock out-

put can be used to synchronize external devices (e.g.,

FPGAs) to the ADC. DCLKP and DCLKN are differential

outputs with LVDS-compatible voltage levels. There is a

4.58ns delay time between the rising (falling) edge of

CLKP (CLKN) and the rising edge of DCLKP (DCLKN).

See Figure 5 for timing details.

Divide-by-2 Clock Control (CLKDIV)

The MAX1213N offers a clock control line (CLKDIV),

which supports the reduction of clock jitter in a system.

Connect CLKDIV to OGND to enable the ADC’s internal

divide-by-2 clock divider. Data is now updated at one-

half the ADC’s input clock rate. CLKDIV has an internal

pulldown resistor and can be left open for applications

that require this divide-by-2 mode. Connecting CLKDIV

to OVCC disables the divide-by-2 mode.

System Timing Requirements

Figure 5 shows the relationship between the clock input

and output, analog input, sampling event, and data out-

put. The MAX1213N samples on the rising (falling)

edge of CLKP (CLKN). Output data is valid on the next

rising (falling) edge of the DCLKP (DCLKN) clock, but

has an internal latency of 11 clock cycles.

Digital Outputs (D0P/N–D11P/N, DCLKP/N,

ORP/N) and Control Input T/B

Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N

are LVDS compatible, and data on D0P/N–D11P/N is

presented in either binary or two’s-complement format

(Table 1). The T/B control line is an LVCMOS-compatible

input, which allows the user to select the desired output

format. Pulling T/B low outputs data in two’s complement

and pulling it high presents data in offset binary format

on the 12-bit parallel bus. T/B has an internal pulldown

resistor and may be left unconnected in applications

using only two’s-complement output format. All LVDS

outputs provide a typical 0.325V voltage swing around a

1.2V common-mode voltage, and must be terminated at

the far end of each transmission line pair (true and com-

plementary) with 100Ω. Apply a 1.7V to 1.9V voltage

supply at OVCC to power the LVDS outputs.

The MAX1213N offers an additional differential output

pair (ORP, ORN) to flag out-of-range conditions, where

out-of-range is above positive or below negative full

scale. An out-of-range condition is identified with ORP

(ORN) transitioning high (low).

Note: Although a differential LVDS output architecture

reduces single-ended transients to the supply and

ground planes, capacitive loading on the digital out-

puts should still be kept as low as possible. Using

LVDS buffers on the digital outputs of the ADC when

driving larger loads may improve overall performance

and reduce system-timing constraints.

SAMPLING EVENT

INP

SAMPLING EVENT

SAMPLING EVENT

SAMPLING EVENT

SAMPLING EVENT

INN

CLKN

CLKP

DCLKN

DCLKP

D0P/D0N–

D11P/D11N

ORP/N

tAD

N

tCPDL

N - 11

tPDL

N - 11

N+1

N - 10

N - 10

tLATENCY

N-9

N + 10

N-1

N-1

N + 11

tCH

tCL

N

N + 12

N+1

N

N+1

tCPDL - tPDL~ 0.4 x tSAMPLE WITH tSAMPLE = 1 / fSAMPLE

NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.

Figure 5. Simplified LVDS Output Architecture

______________________________________________________________________________________ 13

Share Link: