MAX5258 データシートの表示（PDF） - Maxim Integrated
部品番号
コンポーネント説明
メーカー
MAX5258 Datasheet PDF : 20 Pages
| |||
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (MAX5259) (continued)
(VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at VDD = +3V, and TA = +25°C.)
PARAMETER
Digital Feedthrough
Digital-to-Analog Glitch Impulse
SYMBOL
CONDITIONS
Code = 00 hex
Code = 80 to code = 7F hex
MIN TYP MAX UNITS
0.1
nV-s
20
nV-S
Signal-to-Noise Plus Distortion
Ratio
SINAD
VREF = 2.5Vp-p at 1kHz centered at 1.5V
code = FF hex
VREF = 2.5Vp-pat 10kHz centered at 1.5V
code = FF hex
65
dB
54
Multiplying Bandwidth
Wideband Amplifier Noise
POWER REQUIREMENTS
Power-Supply Voltage
Supply Current
Shutdown Supply Current
VREF = 0.1Vp-p centered at VDD/2, -3dB
bandwidth
VDD
IDD
ISHDN
700
kHz
60
µV
2.7
3.6
V
1.3
2.6
mA
0.24
10
µA
TIMING CHARACTERISTICS (MAX5258)
(VREF = +4.096V, GND = 0, CDOUT = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and
TA = +25°C.)
PARAMETER
VDD Rise-to-CS Fall-Setup Time
LDAC Pulse Width Low
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
CS Pulse Width High
SCLK Clock Frequency (Note 5)
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall-to-SCLK Rise-Setup Time
SCLK Rise-to-CS Rise-Hold Time
DIN to SCLK Rise-to-Setup Time
DIN to SCLK Rise-to-Hold Time
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
SYMBOL
tVDCS
tLDAC
tCLL
tCSW
fCLK
tCH
tCL
tCSS
tCSH
tDS
tDH
tDO1
CONDITIONS
MIN TYP MAX UNITS
5
µs
40
20
ns
40
ns
90
10
40
40
40
0
40
0
ns
MHz
ns
ns
ns
ns
ns
ns
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
CS Rise-to-SCLK Rise-Setup
Time
tDO2
tCS1
210
ns
40
ns
_______________________________________________________________________________________ 5
Share Link: 