MAX5942BCSE データシートの表示（PDF） - Maxim Integrated

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MAX5942BCSE

IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices

Maxim Integrated 

IEEE 802.3af Power-Over-Ethernet

Interface/PWM Controller for Power Devices

The PSE determines the class of a PD by applying a volt-

age at the PD input and measures the current sourced

out of the PSE. When the PSE applies a voltage between

12.6V and 20V, the MAX5942A/MAX5942B exhibit a cur-

rent characteristic with values indicated in Table 2. The

PSE uses the classification current information to classify

the power requirement of the PD. The classification cur-

rent includes the current drawn by the 25.5kΩ detection

signature resistor and the supply current of the

MAX5942A/MAX5942B so that the total current drawn by

the PD is within the IEEE 802.3af standard figures. The

classification current is turned off whenever the device is

in power mode.

Power Mode

During power mode, when VIN rises above the undervolt-

age lockout threshold (VUVLO,ON), the MAX5942A/

MAX5942B gradually turn on the internal N-channel MOS-

FET Q1 (see Figure 2). The MAX5942A/MAX5942B

charge the gate of Q1 with a constant current source

(10µA, typ). The drain-to-gate capacitance of Q1 limits

the voltage rise rate at the drain of MOSFET, thereby limit-

ing the inrush current. To reduce the inrush current, add

external drain-to-gate capacitance (see the Inrush

Current section). When the drain of Q1 is within 1.2V of its

source voltage and its gate-to-source voltage is above

5V, the MAX5942A/MAX5942B assert the PGOOD/

PGOOD outputs. The MAX5942A/MAX5942B have a wide

UVLO hysteresis and turn-off deglitch time to compensate

for the high impedance of the twisted-pair cable.

Undervoltage Lockout

The MAX5942A/MAX5942B operate up to a 67V supply

voltage with a default UVLO turn-on set at 39V and a

UVLO turn-off set at 30V. Adjust the UVLO threshold

using a resistor-divider connected to UVLO (see Figure

3). When the input voltage is above the UVLO threshold

(VUVLO,ON), the IC is in power mode and the MOSFET is

on. When the input voltage goes below the UVLO thresh-

old (VUVLO,OFF) for more than tOFF_DLY, the MOSFET

turns off.

To adjust the UVLO threshold, connect an external

resistor-divider from GND to UVLO and from UVLO to

VEE. Use the following equations to calculate R1 and

R2 for a desired UVLO threshold:

R2 = 25.5kΩ x VREF, UVLO

VIN,EX

R1 = 25.5kΩ - R2

where VIN,EX is the desired UVLO threshold. Since the

resistor-divider replaces the 25.5kΩ PD detection resis-

tor, ensure that the sum of R1 and R2 equals 25.5kΩ

VIN = 24V TO 60V

GND

R1

UVLO

MAX5942A

MAX5942B

R2

VEE

Figure 3. Setting Undervoltage Lockout with an External

Resistor-Divider

±1%. When using the external resistor-divider, the

MAX5942 has an external reference voltage hysteresis of

20% (typ). In other words, when UVLO is programmed

externally, the turn-off threshold will be 80% (typ) of the

new UVLO turn-on threshold.

Inrush Current Limit

The MAX5942A/MAX5942B charge the gate of the inter-

nal MOSFET with a constant current source (10µA, typ).

The drain-to-gate capacitance of the MOSFET limits the

voltage rise rate at the drain, thereby limiting the inrush

current. Add an external capacitor from GATE to OUT

to further reduce the inrush current. Use the following

equation to calculate the inrush current:

IINRUSH

=

IG

x

COUT

CGATE

The recommended inrush current for a PoE application

is 100mA.

PGOOD/PGOOD Outputs

PGOOD is an open-drain, active-high logic output.

PGOOD goes high impedance when VOUT is within 1.2V

of VEE and when GATE is 5V above VEE. Otherwise,

PGOOD is pulled to VOUT (given that VOUT is at least 5V

below GND). Connect PGOOD to SS_SHDN to enable

the PWM controller.

PGOOD is an open-drain, active-low logic output.

PGOOD is pulled to VEE when VOUT is within 1.2V of VEE

and when GATE is 5V above VEE. Otherwise, PGOOD

goes high impedance.

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