MAX6951EEE データシートの表示（PDF） - Maxim Integrated

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MAX6951EEE

Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers

Maxim Integrated 

Serially Interfaced, +2.7V to +5.5V,

5- and 8-Digit LED Display Drivers

Table 17. Digit Register Mapping with

Blink Globally Disabled

SEGMENT’S

BIT SETTING

IN PLANE P1

X

X

SEGMENT’S

BIT SETTING

IN PLANE P0

0

1

SEGMENT

BEHAVIOR

Segment off during both

halves of each blink

period

Segment off during both

halves of each blink

period

Table 18. Digit Register Mapping with

Blink Globally Enabled

SEGMENT’S

BIT SETTING

IN PLANE P1

0

0

1

1

SEGMENT’S

BIT SETTING

IN PLANE P0

0

1

0

1

SEGMENT

BEHAVIOR

Segment off

Segment on only during

the 1st half of each blink

period

Segment on only during

the 2nd half of each blink

period

Segment on

be unable to regulate the current correctly. As the sup-

ply voltage drops further, the LED segment drive cur-

rent becomes effectively limited by the output drivers'

on-resistance, and the LED drive current drops. The

characteristics of each individual LED in a modern 7-

segment digit usually match well, so the result is that

the display intensity dims uniformly as supply voltage

drops out of regulation and beyond. The MAX6950/

MAX6951 operate down to 2V supply voltage (although

most displays are very dim at this voltage), providing

that the MAX6950/MAX6951 are powered up initially to

at least 2.7V to trigger the device's internal reset, and

also that the SPI interface is constrained to 5Mbps.

Computing Power Dissipation

The upper limit for power dissipation (PD) for the

MAX6950/MAX6951 is determined from the following

equation:

PD = (V+ x I+) + (V+ - VLED) (DUTY ✕ ISEG ✕ N)

Where:

V+ = supply voltage

DUTY = duty cycle set by intensity register

N = number of segment driven (worst case is 8)

VLED = LED forward voltage

ISEG = segment current set by RSET

PD = power dissipation, in mW if currents are in mA

Dissipation example:

ISEG = 40mA, N = 8, Duty = 15/16, VLED = 2.4V at

40mA, V+ = 3.6V

PD = 3.6V (15mA) + (3.6V - 2.4V)(15 / 16 ✕ 40mA x 8)

= 0.414W

Thus, for the 16-pin QSOP package (TJA = 1/0.00834 =

+120°C/W), the maximum allowed ambient temperature

TA is given by:

TJ (MAX) = TA + (PD ✕ TJA) = +150°C = TA + (0.44 ✕

+120°C/W)

So TA = +100°C. Thus, the device can be operated

safely at a maximum package temperature of +85°C.

Power Supplies

The MAX6950/MAX6951 operate from a single +2.7V to

+5.5V power supply. Bypass the power supply to

ground with a 0.1µF capacitor as close to the pin as

possible. Add a 22µF capacitor if the MAX6950/

MAX6951 are not close to the board’s input bulk decou-

pling capacitor.

Connect the underside exposed pad to GND.

Board Layout

When designing a board, use the following guidelines:

1. The RSET connection to pin 7 is a high-impedance

node, and sensitive to layout. Place RSET right next

to pins 7 and 8 and route RSET directly to these pins

with very short tracks.

2. Ensure that the track from the ground end of RSET

routes directly to pin 8, and that this track is not

used as part of any other ground connection.

Figure 5 shows a good layout. The decoupling capaci-

tors C1 (ceramic) and C2 (bulk, if required) are located

above the IC. The ground track to RSET is a separate

track from both the IC's power ground connection and

the ground plane.

16 ______________________________________________________________________________________

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