MAX8790A データシートの表示（PDF） - Maxim Integrated

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MAX8790A

Six-String White LED Driver with Active Current Balancing for LCD Panel Applications

Maxim Integrated 

MAX8790A

Six-String White LED Driver with Active

Current Balancing for LCD Panel Applications

In digital dimming mode, the step-up controller and cur-

rent source are directly turned on and off by the PWM sig-

nal. The current pulse magnitude, or full-scale current, is

set by ISET and is independent of PWM duty factor. The

current-source outputs are PWM signals synchronized to

the BRT input signal (see Figure 5).

The full-scale current in both methods is specified by

resistance from the ISET pin to ground:

ILEDmax

=

20mA × 100kΩ

RISET

The acceptable resistance range is 74kΩ < RISET <

133kΩ, which corresponds to full-scale LED current of

27mA > ILEDmax > 15mA. Connect ISET to VCC for a

default full-scale LED current of 20mA. When ENA is high,

the analog dimming is enabled, when ENA is low, digital

dimming is enabled.

When the current-source output is pulse-width modulated,

current-source turn-on is synchronized with the BRT

signal. Synchronization and low jitter in the PWM sig-

nals help reduce flicker noise in the display. The current

through each FB_ pin is controlled only during the step-up

converter’s on-time. During the converter’s offtime, the

current sources are turned off. The output voltage does

not discharge and stays high. Each FB_ pin can withstand

28V, which is the pin’s maximum rated voltage.

Table 2 summarizes the characteristics of both analog

and digital dimming methods.

A PLL translates the duty cycle of the BRT input into a

reference for the MAX8790A’s current sources. A resistor

from the FSET pin to ground controls the PLL’s freerun-

ning frequency:

f

PLL

=

10

1

× RFSET

×

800pF

The PLL’s loop filter bandwidth is set with a capacitor from

the CPLL pin to ground. This filter integrates the phase

difference between the BRT input signal and the PLL oscil-

lator. The filter bandwidth determines the PLL’s dynamic

response to frequency changes in the BRT signal. For

most applications, a 0.1μF capacitor is adequate for oscil-

lator frequencies in the 166Hz < fPLL < 500Hz range. The

PLL frequency capture window is 0.6 x fPLL to fPLL.

D = tON

tBRT

BRT

D = 50%

tON

tBRT

D = 30%

DPWM DIMMING MODE

D = 12.5%

D = 6.25%

ILEDMAX

ILED

0A

Figure 5. LED Current Control Using DPWM Dimming Mode

Table 2. Dimming Mode

MODE

Analog + DPWM

Direct DPWM

ENA

PLL FREQUENCY

CPLL

DESCRIPTION

Analog dimming from 100% to 12.5% brightness. From 12.5% to

> 2.1V 250kΩ < RFSET < 754kΩ 0.1µF 1% brightness, DPWM dimming is employed. BRT frequency range

is 100Hz to 500Hz.

< 0.8V

VFSET > VCC - 0.4V,

disables PLL

OPEN

Direct dimming by BRT signal. BRT frequency can be 100Hz to

2kHz; 50µs minimum BRT on-time limits the minimum brightness.

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