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MB86961APF-G データシートの表示(PDF) - Fujitsu
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MB86961APF-G
UNIVERSAL INTERFACE FOR 10BASE -T
Fujitsu
MB86961APF-G Datasheet PDF : 29 Pages
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MB86961A
MODE 1 (MD1=0, MD0=0) TIMING DIAGRAMS — FIGURES 12 - 17
TPIP/TPIN
CD
10101010111010001010
t
CD
RCLK
RXD
t
DATA
t
RDH
t
RDS
1 0 1 0 1 0 1 0 1 1 1 01
Figure 12. Mode 1 RCLK/SOP Timing
TPIP/TPIN
101010100
CD
t
RD
t
CDOFF
t
IFG
RCLK
RXD
101010100
Note: RXD is triggered by the rising edge of RCLK, with RCLK advanced by 25 ns. The controller is sampled at the rising edge.
Figure 13. Mode 1 RCLK/EOP Timing
19
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