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MB89850R データシートの表示(PDF) - Fujitsu

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MB89850R Datasheet PDF : 48 Pages
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MB89850R Series
(Continued)
Address
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H to 7BH
7CH
7DH
7EH
7FH
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R)
(R)
(W)
(W)
(W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
(R/W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Register name
EIC1
EIC2
ADC1
ADC2
ADDH
ADDL
ZOCTR
CLRBRH
CLRBRL
TCSR
CICR
TMCR
COER
CMCR
DTCR
DTSR
OCTBR
OCPBR0H
OCPBR0L
OCPBR1H
OCPBR1L
OCPBR2H
OCPBR2L
OCPBR3H
OCPBR3L
ILR1
ILR2
ILR3
Register description
External interrupt control register 1
External interrupt control register 2
A/D converter control register 1
A/D converter control register 2
A/D converter data register (H)
A/D converter data register (L)
Vacancy
Zero detection output control register
Compare clear buffer register (H)
Compare clear buffer register (L)
Timer control status register
Compare interrupt control register
Timer mode control register
Compare/port selection register
Compare buffer mode control register
Dead-time timer control register
Dead-time setting register
Output control buffer register
Output compare buffer register 0 (H)
Output compare buffer register 0 (L)
Output compare buffer register 1 (H)
Output compare buffer register 1 (L)
Output compare buffer register 2 (H)
Output compare buffer register 2 (L)
Output compare buffer register 3 (H)
Output compare buffer register 3 (L)
Vacancy
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
Notes: • Do not use vacancies.
• When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register
containing a write-only bit, a bit designated by the instruction will have a predetermined value. However,
a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access
to the register should be tried with any read-modefy-write instruction.
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