MB89950 データシートの表示（PDF） - Fujitsu

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MB89950

8-bit Proprietary Microcontroller

Fujitsu 

s BLOCK DIAGRAM

X0

X1

Oscillator

Clock control

RST

Reset circuit

(WDT)

P00/SEG20 to 8

P07/SEG27

P10/SEG28 to 8

P17/SEG35

SEG0 to SEG19

COM0 to COM3

V3

P20/SEG36 to 6

P25/SEG41

P33/V2

P32/V1

P30

P31

N-ch open-drain I/O port

20

4

LCD controller/driver

N-ch open-drain I/O port

R A M (256 × 8 bits)

F2MC-8L

CPU

R O M (8 K × 8 bits)

MB89950 Series

20-bit

timebase timer

8-bit PWM timer

External interrupt

8-bit

pulse width

counter

timer

Noise

clear

8-bit serial I/O

UART

CMOS I/O port

P41/PWM

P40

P42/PWC/

INT1

P45/SCK

P44/SO

P43/SI

P46/INT0

Other pins

MODA

VCC, VSS

17

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