MB90F543 データシートの表示（PDF） - Fujitsu
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MB90F543 Datasheet PDF : 67 Pages
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MB90540/540G/545/545G Series
(8) Hold Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):
VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol Pin name Condition
Value
Units Remarks
Min
Max
Pin floating→HAK↓time
tXHAL
HAK
30
tCP
ns
HAK↑time→Pin valid time
tHAHV
HAK
tCP
2 tCP
ns
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.
• Hold Timing
HAK
Each pin
tXHAL
2.4 V
0.8 V
0.8 V
2.4 V
High impedance
tHAHV
2.4 V
0.8 V
(9) UART0/1, Serial I/O Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S):
VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol Pin name
Condition
Value
Units Remarks
Min Max
Serial clock cycle time
tSCYC SCK0 to SCK2
8 tCP ns
SCK↓→SOT delay time
Valid SIN→SCK↑
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
Internal clock opera-
−80
80
ns
tIVSH
SCK0 to SCK2, tion output pins are
SIN0 to SIN2 CL = 80 pF + 1 TTL.
100
ns
SCK↑→Valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60 ns
Serial clock “H” pulse width
tSHSL SCK0 to SCK2
4 tCP ns
Serial clock “L” pulse width
tSLSH SCK0 to SCK2
4 tCP ns
SCK↓→SOT delay time
Valid SIN→SCK↑
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
External clock oper-
ation output pins are
150
ns
tIVSH
SCK0 to SCK2, CL = 80 pF + 1 TTL.
SIN0 to SIN2
60
ns
SCK↑→Valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60 ns
Note : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• For tCP (Machine clock cycle time) , refer to “ (1) Clock Timing”.
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