MB90560 データシートの表示（PDF） - Fujitsu

部品番号

コンポーネント説明

メーカー

MB90560

16-bit Proprietary Microcontrollers(CMOS)

Fujitsu 

MB90560/565 Series

• Figure 2 Timing chart for ports 0 and 1 going to high impedance state (When RST pin level is “L”)

VCC (Power supply pin)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operating clock A) signal

KB (Internal operating clock B) signal

PORT (port output) signal

Oscillation stabilization delay time*2

Regulator circuit

stabilization delay time*1

High impedance

*1 : Regulator circuit oscillation stabilization delay time :

217/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time :

218/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency)

(10) Notes on using the DIV A, Ri and DIVW A, RWi instructions

The location in which the remainder value produced by the signed division instructions “DIV A, Ri” and “DIVW

A, RWi” is stored depends on the bank register. The remainder is stored in an address in the memory bank

specified in the bank register.

Set the bank register to “00H” when using the “DIV A, Ri” and “DIVW A, RWi” instructions.

(11) Notes on using REALOS

The extended intelligent I/O service (EI2OS) cannot be used when using REALOS.

(12) Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-

running frequency of the self oscillation circuit in the PLL circuitry even if the oscillator is out of place or the clock

input is stopped. Performance of this operation, however, cannot be guaranteed.

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DS07-13715-5E

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