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MB91F109 データシートの表示(PDF) - Fujitsu

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MB91F109 Datasheet PDF : 117 Pages
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MB91F109
s BLOCK DIAGRAM
FR CPU
RAM (2 Kbytes)
DREQ0 to
DREQ2
DACK0 to
DACK2
EOP0 to
EOP2
Bit search module
3
3 DMA controller (DMAC)
3
(8 ch.)
Bus converter (32 bits16bits)
X0
X1
RST
Clock control unit
(Watchdog timer)
Bus converter
(HarvardPrinceton)
Bus controller
16 D16 to D31
25 A00 to A24
2
RD
WR0, WR1
RDY
6
CLK
CS0 to CS5
BRQ
BGRNT
INT0 to INT3 4
NMI
4
AN0 to AN3
AVCC
AVSS
AVRH
AVRL
ATG
Interrupt control unit
10-bit A/D converter
(4 ch.)
DRAM interface
Flash memory
254k
RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0
DW1
16-bit reload timer (3 ch.)
RAM 2 Kbytes
PE0 to PE7
PF0 to PF7
8
8
Port E,
Port F
Other pins
MD0 to MD2, VCC, VSS
Port 2 to port B
UART (3 ch.)
(Baud rate timer)
8
P20 to P27
8
P30 to P37
8
P40 to P47
8
P50 to P57
8
P60 to P67
P70
6
PA80 to P85
7
PA0 to PA6
8
PB0 to PB7
3
SI0 to SI2
3 SO0 to SO2
3 SC0 to SC2
PWM timer (4 ch.)
4
OCPA0 to OCPA3
4 TRG0 to TRG3
Note : Pins are display for functions (Actually some pins are multiplexer).
When using REALOS, time control should be done by using external interrupt or inner timer.
19

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