MB91F191A データシートの表示（PDF） - Fujitsu
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MB91F191A Datasheet PDF : 33 Pages
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MB91191/192 Series
(2) Multiplex Bus Read/Write Operation
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Parameter
Symbol Pin Name
Condi-
tion
Min
Value
Typ
Max
Unit
Re-
marks
ALE pulse width
tEHEL ALE
tCYC − 10
ns
Address delay time
Address clear time
tEHAV
tEHAX
A15 to A0,
D31 to D16
tCYCH − 15 tCYCH tCYCH + 15 ns *2
tCYCL − 2
tCYCL tCYCL + 10 ns *2
Data delay time
tELDV D31 to D16
tCYCL + 26 ns *2
RD delay time
RD pulse width
tELRL
RD
tRLRH
tCYC − 11
tCYC
tCYC + 11 ns
tCYC − 11
tCYC
tCYC + 11 ns *1
WR0, WR1 delay time
tELWL
tCYC − 11
tCYC
tCYC + 11 ns
WR0, WR1
WR0, WR1 pulse width
tWLWH
tCYC − 11
tCYC
tCYC + 11 ns *1
Data setup → RD ↑ time tDSRH RD,
RD ↑→ Data hold time
tRHDX D31 to D16
15
ns
0
ns
*1 : When the bus is delayed by automatic wait insertion, add (tCYC × number of wait cycles) to this value.
*2 : This value is for gear setting = ×1
For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below.
Formula : tCYCH = (1 − n / 2) × tCYC
tCYCL = (n / 2) × tCYC
Internal
clock
ALE
Read time
D31 to D16
MPX bus
RD
Write time
D31 to D16
MPX bus
WR0 , WR1
A15 to A08
When not
multiplexed
tEHEL
tEHAV
tELAX
tDSRH
tRHDX
tELRL
tELDV
tELWL
tRLRH
tWHDX
tWLWH
21
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