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MB91220/S データシートの表示(PDF) - Fujitsu

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MB91220/S
Fujitsu
Fujitsu Fujitsu
MB91220/S Datasheet PDF : 88 Pages
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MB91220/S Series
HANDLING DEVICES
Preventing Latch-up
Latch-up may occur in a CMOS IC, if a voltage greater than VCC or less than VSS is applied to input and output
pin, or if an above-rating voltage is applied between VCC and VSS pins. When latch-up occurs, it may significantly
increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS
IC, be very careful not to exceed the maximum rating.
Treatment of Unused Input Pins
Do not leave unused input pins open, as this may cause a malfunction. Handle by performing a pull-up or pull-
down with a resistance of 2 kor more. An unused I/O pin should be set to the output status and left open.
When set to the input status, it should be handled in the same way as an input pin.
Power supply pins
If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential
are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the
pins to the external power supply and ground lines to lower the electro-magnetic emission level, to prevent
abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output
current rating. Moreover, connect the current supply source to the VCC and VSS pins of this device via a low
impedance.
Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC
and VSS near this device.
This device incorporates a regulator. When using the device with 5 V power supply, apply that power supply to
the VCC pin and always connect the VCC3C pin to a capacitor with 1 µF or more for the purpose of regulator.
Example of power supply connection
5V
5V
5V
GND
VCC
DVCC
AVCC
AVRH
AVSS
VSS
DVSS
VCC3C
1 µF
20

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