29LV650 データシートの表示（PDF） - Fujitsu

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コンポーネント説明

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29LV650

FLASH MEMORY CMOS 64M (4M x 16) BIT

Fujitsu 

MBM29LV650UE/651UE-90/12

Word Programming

The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are

two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses

are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge

of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins

programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required

to provide further controls or timings. The device will automatically provide adequate internally generated

program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ7 (Data Polling), and DQ6 (Toggle

Bit). The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 8, Hardware

Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system

at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being

programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the

programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1” Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0” Only

erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ7 (Data Polling), and DQ6 (Toggle Bit).

The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence

and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device

returns to read the mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.

After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.

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