MBM29LV800BE90PCV データシートの表示（PDF） - Fujitsu

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MBM29LV800BE90PCV

FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT

Fujitsu 

MBM29LV800TE/BE60/70/90

s COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

“MBM29LV800TE/BE Command Definitions” in “s DEVICE BUS OPERATION” defines the valid register com-

mand sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while

the Sector Erase operation is in progress. Furthermore both Read/Reset commands are functionally equivalent,

resetting the device to the read mode. Note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8

bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The devices remain enabled for reads until the command

register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-

istics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such

manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-

grammers typically access the signature codes by raising A9 to a high voltage. However multiplexing high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read

cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29LV800TE = DAh and MBM29LV

800BE = 5Bh for ×8 mode; MBM29LV800TE = 22DAh and MBM29LV800BE = 225Bh for ×16 mode) .

(See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table”

in “s DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd parity with DQ7 defined

as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h for ×16 (XX04h

for ×8).

Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a

logical “1” at device output DQ0 for a protected sector. The programming verification should be performed margin

mode on the protected sector. (See “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV

800TE/BE User Bus Operations (BYTE = VIL)” in “s DEVICE BUS OPERATION”.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To

execute the Autoselect command during the operation, writing Read/Reset command sequence must precede

the Autoselect command.

Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle

operation. There are two “unlock” write cycles. These are followed by the program set-up command and data

write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is

latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever

happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,

the system is not required to provide further controls or timings. The device will automatically provide adequate

internally generated program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware

Sequence Flags”.) Therefore, the devices require that a valid address to the devices be supplied by the system

at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being

programmed.

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