MBM29PL160BD データシートの表示（PDF） - Fujitsu

部品番号

コンポーネント説明

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MBM29PL160BD

16M (2M × 8/1M × 16) BIT

Fujitsu 

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

DQ2

Toggle Bit II

This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2

to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address

of the non-erase suspended sector will indicate a logic “1” at DQ2.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress.

For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also Table 10 and Figure 15.

Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ2 toggles if this bit is read from an erasing sector.

Table 10 Toggle Bit Status

Mode

DQ7

DQ6

DQ2

Program

DQ7

Toggle

1

Erase

0

Toggle

Toggle

Erase Suspend Read

(Erase Suspended Sector)

1

(Note 1)

1

Toggle

Erase-Suspend Program

DQ7

Toggle (Note 1)

1 (Note 2)

Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to

toggle.

Word/Byte Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29PL160TD/BD device. When

this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0

to DQ15. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin

becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. Refer to

Figures 11 to 13 for the timing diagrams.

Data Protection

The MBM29PL160TD/BD is designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the device automatically

resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up

and power-down transitions or system noise.

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