MC10H171FN データシートの表示（PDF） - ON Semiconductor
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MC10H171FN Datasheet PDF : 5 Pages
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MC10H171
Dual Binary to 1−4 Decoder
(Low)
Description
The MC10H171 is a binary coded 2 line to dual 4 line decoder with
selected outputs low. With either E0 or E1 high, the corresponding
selected 4 outputs are high. The common enable E, when high, forces
all outputs high.
Features
• Propagation Delay, 2 ns Typical
• Power Dissipation 325 mW Typical (same as MECL 10K™)
• Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K Compatible
• Pb−Free Packages are Available*
E0 14
LOGIC DIAGRAM
10 Q0 3
11 Q0 2
12 Q0 1
A9
VCC1 = PIN 1
13 Q0 0 VCC2 = PIN 16
3 Q1 3 VEE = PIN 8
B7
4 Q1 2
E 15
5 Q1 1
E1 2
6 Q1 0
DIP
PIN ASSIGNMENT
VCC1
1
E1
2
Q13
3
Q12
4
Q11
5
Q10
6
B
7
VEE
8
16
VCC2
15
E
14
E0
13
Q00
12
Q01
11
Q02
10
Q03
9
A
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING DIAGRAMS*
16
1
16
MC10H171P
AWLYYWWG
1
PDIP−16
P SUFFIX
CASE 648
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
10H171G
AWLYYWW
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
March, 2006 − Rev. 7
Publication Order Number:
MC10H171/D
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