33099 データシートの表示（PDF） - Motorola => Freescale
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33099 Datasheet PDF : 18 Pages
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TYPICAL APPLICATIONS
circuitry to limit the lamp drive and regulates the lamp current
to current Idsc. When the power dissipation of the lamp driver
causes the temperature of the lamp driver to exceed a
thermal shut-down temperature limit (TLim), a temperature
sensing diode (Dtl) causes the thermal limit circuitry to send
a signal to the lamp driver circuitry to limit the lamp drive
current and reduce the power dissipation and resulting
device temperature. When the lamp driver is ON, but the
Lamp Drain pin voltage is not below the BAT pin voltage Vbat
by at least a lamp drain short circuit threshold voltage (VTdsc)
or ([Vbat - Vdrain] < VTdsc), comparator Cds will output a lamp
short circuit signal to the Drain Polling circuit to indicate a
lamp shorted condition. The Drain Polling circuit provides a
low duty cycle polling output to the input of the AND2 GATE
to poll the lamp driver ON, continuously testing for a lamp
short without damaging the lamp driver. The polling duty
cycle is 1.56%, (or about a 158 µs ON pulse) at a frequency
of fmsb/4, or 98.6 Hz. After the lamp short has been removed,
the comparator Cds outputs a lamp not-shorted signal to the
Drain Polling circuitry, which provides a logic [1] to the AND2
GATE, which then operates normally.
Lamp polling is also present when the lamp is ON. In this
case, lamp polling turns OFF the lamp for a short period of
time with the lamp being ON for the remainder of the time. In
this case the lamp ON duty cycle is 98.44% (or OFF for
158 µs) at a frequency of fmsb /4, or 98.6 Hz. This causes the
lamp voltage on the lamp drain pin to be greater than ignition
threshold voltage VTign for at least 158 µs of a 10.1 ms
period. During the lamp ON mode, the Ignition Turn Off Delay
of the Ignition Delay circuit is greater then the 10.1 ms period.
As a result, the regulator biasing remains ON even when the
IGN pin is coupled to the LAMP DRAIN pin and the lamp
drain voltage is less than voltage VTign most of the time when
the lamp is ON.
The lamp driver is also protected from load dump, since
during load dump, the LD signal is a logic [0], preventing the
AND2 GATE from activating the lamp driver. In addition, a
drain-to-GATE clamp device Z2 limits the drain-to-GATE
clamping voltage (Vdg) to about 40 V typically.
UNDERVOLTAGE, OVERVOLTAGE, AND LOAD
DUMP PROTECTION
An undervoltage, overvoltage and load dump condition is
sensed by the regulator to generate fault indications and to
protect the regulator and associated external devices. As
previously discussed, a load dump signal during load dump
will prevent GATE drive to the external MOSFET and prevent
GATE drive to the lamp driver. Thus the external and internal
MOSFETs will turn OFF during a system load dump. As
previously discussed, the undervoltage and overvoltage
signals are also provided for fault indications.
The undervoltage signal is provided on the UV line by an
undervoltage comparator Cuv having a voltage reference of
1.25 V and a resistor divider voltage transfer of 1.26 from the
FB output to comparator Cuv input. When voltage Vfb on the
FB output becomes less than 1.52 V, the voltage at input to
comparator Cuv becomes less than 1.25 V, causing
comparator Cuv to output an undervoltage UV signal.
Because voltage Vfb is ideally voltage Vrs (or voltage Vls),
and the ratio of Vr/Vrs (or Vl/Vls) is 7.45, the UV signal will
occur when the system voltage at the Remote input (or Local
input) is less than an undervoltage threshold voltage (VTuv),
or 11.35 V. However, GATE AND1 ensures that frequency
fph must be greater than f2 before an undervoltage Fault is
indicated by the lamp.
The load dump and overvoltage detection also utilizes
similar resistor dividers and voltage comparators in an
Overvoltage Detect circuitry where all comparators are
referenced to voltage Vref, or about 2.0 V. When voltage Vfb
on the FB output is greater than 2.58 V, or 1.29 Vref (Vfb / Vref
= 1.29), an output load dump signal of a logic [0] is generated
on the LD line. Thus during load dump, voltage Vrs (or Vlocal)
will be about 2.58 V, and the actual load dump threshold
voltage (VTld) will be about 19.25 V, or 1.3 Vset. When
voltage Vfb on the FB output is greater than 1.117 Vref (Vfb/
Vref = 1.117), an output overvoltage signal is generated on
the OV line. Thus voltage Vrs (or Vl) will be about 2.235 V,
and the actual overvoltage threshold voltage (VTov) will be
about 16.65 V, or 1.125 Vset.
The regulator also indicates an overvoltage condition on
the system during the Remote fault condition when the
remote wire resistance increases to a finite value and the
system voltage is being regulated by secondary regulation at
Vset2. When a load dump occurs during secondary
regulation, the load dump threshold increases to 1.3 Vset2, or
about 24 V.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33099
15
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