Application Note
Freescale Semiconductor, Inc.
$0001 Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
See
Note
See
Note
PB3
PB2
See
See
Note Note
Reset:
Unaffected by reset
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will en-
sure that the pulldown devices are enabled, thus properly terminating them.
Figure 7. Port B Data Register (PORTB)
$0005 Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
See
Note
See
Note
DDRB3 DDRB2
See
Note
See
Note
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will en-
sure that the pulldown devices are enabled, thus properly terminating them.
Figure 8. Port B Data Direction Register (DDRB)
$0011 Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
See
Note
See
Note
PDIB3 PDIB2
See
Note
See
Note
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are avail-
able for read/write but are not available externally. Configuring them as inputs will en-
sure that the pulldown devices are enabled, thus properly terminating them.
Figure 9. Pulldown Register B (PDRB)
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Go to: www.freescale.com
AN1746