MCF51JF128(2011) データシートの表示（PDF） - Freescale Semiconductor

部品番号

コンポーネント説明

メーカー

MCF51JF128
(Rev.:2011)

Embedded - Microcontrollers

Freescale Semiconductor 

Num

EP9

Memories and memory interfaces

Table 20. EzPort switching specifications (continued)

Description

EZP_CS negation to EZP_Q tri-state

Min.

Max.

Unit

—

12

ns

EZP_CK

EZP_CS

EZP_Q (output)

EZP_D (input)

EP3

EP4

EP2

EP9

EP7

EP8

EP5

EP6

Figure 6. EzPort Timing Diagram

6.4.3 Mini-Flexbus Switching Specifications

All processor bus timings are synchronous; input setup/hold and output delay are given in

respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be

the same as the internal system bus frequency or an integer divider of that frequency.

The following timing numbers indicate when data is latched or driven onto the external

bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships

can be derived from these values.

Table 21. Flexbus switching specifications

Num

FB1

FB2

FB3

FB4

FB5

Description

Operating voltage

Frequency of operation

Clock period

Address, data, and control output valid

Address, data, and control output hold

Data and FB_TA input setup

Data and FB_TA input hold

Min.

2.7

—

20

TBD

1

20

10

Max.

3.6

25

—

20

—

—

—

Unit

V

MHz

ns

ns

ns

ns

ns

Notes

1

1

2

2

MCF51JF128 Advance Information Data Sheet, Rev. 2, 05/2011.

Freescale Semiconductor, Inc.

Preliminary

31

Share Link: