MCP1725 データシートの表示（PDF） - Microchip Technology

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MCP1725

500 mA, Low Voltage, Low Quiescent Current LDO Regulator

Microchip Technology 

The maximum power dissipation capability for a

package can be calculated given the junction-to-

ambient thermal resistance and the maximum ambient

temperature for the application. Equation 5-4 can be

used to determine the package maximum internal

power dissipation.

EQUATION 5-4:

PD(MAX) = -(--T---J---(--M----A---X--R-)---θ–---J--T-A---A---(--M----A---X---)--)-

PD(MAX) = Maximum device power dissipation

TJ(MAX) = maximum continuous junction

temperature

TA(MAX) = maximum ambient temperature

RθJA = Thermal resistance from junction to

ambient

EQUATION 5-5:

TJ(RISE) = PD(MAX) × RθJA

TJ(RISE) = Rise in device junction temperature

over the ambient temperature

PD(MAX) = Maximum device power dissipation

RθJA = Thermal resistance from junction to

ambient

EQUATION 5-6:

TJ = TJ(RISE) + TA

TJ = Junction temperature

TJ(RISE) = Rise in device junction temperature

over the ambient temperature

TA = Ambient temperature

MCP1725

5.3 Typical Application

Internal power dissipation, junction temperature rise,

junction temperature and maximum power dissipation

is calculated in the following example. The power dissi-

pation as a result of ground current is small enough to

be neglected.

EXAMPLE 5-1:

POWER DISSIPATION

EXAMPLE

Package

Package = 2x3 DFN

Type

Input Voltage

VIN = 3.3V ± 5%

LDO Output Voltage and Current

VOUT = 2.5V

IOUT = 0.5A

Maximum Ambient Temperature

TA(MAX) = 60°C

Internal Power Dissipation

PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x

IOUT(MAX)

PLDO = ((3.3V x 1.05) – (2.5V x 0.975))

x 0.5A

PLDO = 0.51 Watts

5.3.1

DEVICE JUNCTION TEMPERATURE

RISE

The internal junction temperature rise is a function of

internal power dissipation and the thermal resistance

from junction-to-ambient for the application. The

thermal resistance from junction-to-ambient (RθJA) is

derived from an EIA/JEDEC standard for measuring

thermal resistance for small surface-mount packages.

The EIA/JEDEC specification is JESD51-7 “High

Effective Thermal Conductivity Test Board for Leaded

Surface-Mount Packages”. The standard describes the

test method and board specifications for measuring the

thermal resistance from junction to ambient. The actual

thermal resistance for a particular application can vary

depending on many factors such as copper area and

thickness. Refer to AN792, “A Method to Determine

How Much Power a SOT23 Can Dissipate in an Appli-

cation” (DS00792), for more information regarding this

subject.

TJ(RISE) = PTOTAL x RθJA

TJRISE = 0.51 W x 76.0° C/W

TJRISE = 38.8°C

© 2007 Microchip Technology Inc.

DS22026B-page 21

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