ML9228 データシートの表示（PDF） - Oki Electric Industry

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ML9228

82-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, Keyscan

Oki Electric Industry 

OKI Semiconductor

FEDL9228-01

ML9228

FUNCTIONAL DESCRIPTION

Power-on Reset

When power is turned on, ML9228 is initialized by the internal power-on reset circuit.

The status of the internal circuit after initialization is as follows:

• The contents of the shift registers and latches are set to “0”.

• The digital dimming duty cycle is set to “0”.

• All segment outputs are set to Low level.

• Grid1 output is set to Low level. Grid2,3 outputs are set to High level.

• All the ROW outputs are set to Low level.

• INT output is set to Low level.

Reset

When power is turned on, ML9228 is initialized by the internal power-on reset circuit.

The status of the internal circuit after initialization is as follows:

• The contents of the shift registers and latches are set to “0”.

• The digital dimming duty cycle is set to “0”.

• All segment outputs are set to Low level.

• Grid1 output is set to Low level. Grid2,3 outputs are set to High level.

• All the ROW outputs are set to Low level.

• INT output is set to Low level.

• A command is received by the signal of Low(L-GND) level.

Blank

All segment outputs are set as a Low level.

• A command is received by the signal of Low(L-GND) level.

Data Input and Output

Data input and output through the DATA-I/O pin is valid only when the CS pin is set at a High level.

The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is

automatically loaded to the latches when the CS pin is set at a Low level.

10-bit dimming data (D1 to D10) and 82-bit segment data (S1 to S82) are used for inputting of dimming data and

display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data

succeddingly.

The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock.

ML9228 outputs 30-bit key data (S11 to S56). To receive these data, the mode data (M0 to M2) must be sent first

and then CS must be set once to Low level and set again to High level.

Then inputting serial clocks, these data are output from the DATA I/O pin.

When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin.

To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is

stopped immediately.

CS

CLOCK

DATA I/O

M0 M1 M2

Keyscan

Stop

Command

M0 M1 M2

Switch

Data

Output

Command

S11 S12 S13 S14 S15 S21 S22 S44 S45 S51 S52 S53 S54 S55 S56

Switch Data

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