TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
IN1, IN2, EN
(GIN)
OUTn
(GOUT)
tPZH*,
tPLH
(tTON)
50%
90%
10%
tPHL
(tTOFF)
* The last state is “Z”.
Figure 4. tPLH, tPHL, and tPZH Timing
Table 5. Truth Table
VDDDETON
VDD
1.5 V
tVDDDET
3.5 V
50%
VDDDETOFF
tVDDDET
90%
IM
0%
(<1.0 µA)
Figure 5. Low-Voltage Detection Timing
INPUT
OUTPUT
EN
IN1
IN2
GIN
OUT1
OUT2
GOUT
H
L
L
X
Z
Z
X
H
H
L
X
H
L
X
H
L
H
X
L
H
X
H
H
H
X
L
L
X
L
X
X
X
L
L
L
H
X
X
L
X
X
H
H
X
X
H
X
X
L
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
The GIN pin and EN pin are pulled up to VDD with internal resistance.
Analog Integrated Circuit Device Data
Freescale Semiconductor
17510
7