MPC9449 データシートの表示（PDF） - Motorola => Freescale
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MPC9449 Datasheet PDF : 12 Pages
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MPC9449
Freescale Semiconductor, Inc.
DSELA
0
VCC
1
CCLK0
0
0
CCLK1
1
÷1
0
1
CCLK_SEL
÷2
1
VCC
PCLK
PCLK
0
1
PCLK_SEL
DSELB
DSELC
0
1
DSELD
MR/OE
QA0
QA1
QB0
QB1
QB2
QC0 NC
4039 38 37 36 35 34 33 32 31 30 29 28 2726
NC
QC1 VCC
41
QB2
42
25
VCC
24
QD4
QC2 GND
43
23
GND
QC3 QB1
44
VCC
45
22
QD3
21
VCC
QD0 QB0
46
MPC9449
20
QD2
GND
47
QD1
GND
48
19
GND
18
QD1
QD2 QA1
49
17
VCC
VCC
50
QD3
QA0
51
16
QD0
15
GND
QD4 GND
52
14
NC
1 2 3 4 5 6 7 8 9 10 11 12 13
QD5
Figure 1. MPC9449 Logic Diagram
Figure 2. MPC9449 52–Lead Package Pinout (Top View)
Table 1: FUNCTION TABLE
Control
Default
0
PCLK_SEL
0
LVCMOS clock input selected (CCLK0 or CCLK1)
CCLK_SEL
0
CCLK0 selected
DSELA, DSELB,
00
÷1
DSELC, DSELD
00
MR/OE
1
Outputs enabled
1
PCLK differential input selected
CCLK1 selected
÷2
Outputs disabled (high impedance)
Table 2: PIN CONFIGURATION
Pin
I/O
PCLK, PCLK
Input
CCLK0, CCLK1
Input
PCLK_SEL
Input
CCLK_SEL
Input
DSELA, DSELB, DSELC, DSELD Input
MR/OE
Input
QA0-1, QB0-2, QC0-3, QD0-5
Output
GND
Supply
VCC
Supply
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
Function
Differential LVPECL clock input
LVCMOS clock inputs
LVPECL clock input select
LVCMOS clock input select
Clock divider selection
Output enable/disable (high-impedance tristate)
Clock outputs
Negative power supply (GND)
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation
MOTOROLA
For More Informa2tion On This Product,
Go to: www.freescale.com
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